# Collaborative Engineering: From Solutions to Commercial Enterprise at Scale


## Liquid Cooling Insights



Collaborative Engineering: From Solutions to Commercial Enterprise at Scale

***By Joe Sullivan, Senior Engineering and Product Development Manager, Mikros Technologies***

**September 16, 2026**





Broadcom announced in February that it had released the first 2nm custom compute SoCs built on its [3.5D XDSiP](https://www.broadcom.com/info/ai/3point5d) extreme-dimension system-in-package platform. This modular, multi-dimensional stacked die combines 2.5D techniques and 3D-IC integration using F2F technology. It is designed to deliver the compute density, memory bandwidth, and interconnect performance required for next-generation hyperscale AI deployments and gigawatt-scale AI clusters. Additionally, XPUs leveraging the same advanced packaging architecture are expected to enter production in the second half of 2026, further increasing compute density and driving demand for high-performance thermal management solutions. Components in this power class fundamentally change the thermal equation. XPU designs are already approaching 5,000 Watts TDPs, driving heat flux and total thermal dissipation well beyond the practical limits of air cooling. At these power densities, a conventional air-cooled solution would require an infeasibly large heat sink, creating unacceptable constraints on board layout, volumetric efficiency, airflow delivery, and system-level power consumption. With board real estate increasingly consumed by voltage regulation modules (VRM), high-bandwidth memory (HBM), high-speed interconnects, and signal routing infrastructure, the thermal overhead associated with air cooling becomes prohibitive. As a result, the industry has largely converged on liquid cooling as a foundational technology, enabling thermal performance, rack densities, and energy efficiency required to support large-scale AI and accelerated computing workloads.

Liquid Cooling Has Earned a Place on Semiconductor Roadmaps

Liquid cooling has become a design assumption in advanced semiconductor roadmaps because transistor scaling, advanced packaging, and compute density are increasing power consumption. As advances in process technology, chiplet architectures, 2.5D and 3D packaging, and HBM enable unprecedented gains in computational density, they also concentrate more power into a smaller footprint and push heat flux higher. Power is a primary design constraint, so it can no longer be treated as a downstream system-consideration. Semiconductor manufacturers recognize that achieving and maintaining performance targets requires co-optimization of silicon, packaging, power delivery, and cooling from the earliest design stages. Liquid cooling adoption is also driven by system-level requirements. AI training and inference workloads reward architectures that maximize compute density while minimizing latency and power consumption. To achieve these objectives, designers are packing more accelerators, memory, and networking resources into each server and rack, driving rack power from tens of kilowatts to hundreds of kilowatts. Air cooling struggles to support these power densities without significant penalties in heat sink volume, airflow requirements, fan power, and system design complexity. As a result, thermal considerations now influence semiconductor roadmaps alongside traditional metrics such as transistor density, memory bandwidth, and interconnect performance. Liquid cooling for data centers, most importantly, is an enabling technology. Future generations of AI processors cannot deliver their intended capabilities if thermal constraints limit clock frequencies, reduce efficiency, or prevent deployment at the rack densities customers require. Hyperscale and cloud providers are increasingly designing facilities around liquid-cooled infrastructure. Semiconductor vendors are responding by developing products optimized for direct-to-chip liquid cooling environments. A cold plate has become an integral part of the technology stack, not just an external system component.

Thermal Requirements Are a First-Order Design Constraint

The trajectory of AI infrastructure makes the thermal challenge obvious. Nvidia's Blackwell platform pushed server rack power to roughly [120 kW](https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing) in Q1 of 2024. Rubin Ultra "Kyber," expected in the second half of 2027, is projected to reach [600 kW](https://www.datacenterdynamics.com/en/news/nvidias-rubin-ultra-nvl576-rack-expected-to-be-600kw-coming-second-half-of-2027/) per server rack. Supporting these next-gen systems requires a new generation of power and cooling infrastructure, including 800 VDC power architecture designed for a path toward [1 MW racks](https://developer.nvidia.com/blog/nvidia-800-v-hvdc-architecture-will-power-the-next-generation-of-ai-factories/) and beyond. Cooling now influences system architecture from the facility level down to the package, board, and component level, shaping how infrastructure must be designed and deployed. Liquid cooling is also a critical enabler of data center energy efficiency. As power densities increase and regulations such as the [EU Energy Efficiency Directive](https://energy.ec.europa.eu/topics/energy-efficiency/energy-efficiency-targets-directive-and-rules/energy-efficiency-directive/energy-performance-data-centres_en#a-data-base-for-reporting) require operators to monitor and report energy performance metrics, hyperscale operators are prioritizing cooling architectures that minimize facility overhead and maximize compute utilization. Unlike air-based systems, liquid cooling leverages the significantly higher volumetric heat capacity and thermal conductivity of liquids to transport heat more efficiently from high-power components. At the facility level, advanced liquid cooling reduces cooling-system energy consumption by enabling higher coolant temperatures, reducing dependence on energy-intensive mechanical refrigeration, and lowering parasitic cooling power associated with heat rejection, including the electrical energy required to operate coolant pumps, fans, and compressors. This improved resource utilization reduces overall data center power consumption and supports sustainability objectives. By optimizing how heat is transferred, dissipated, and recovered, liquid cooling contributes to improved Power Usage Effectiveness (PUE), the industry's primary metric for measuring data center efficiency. Additionally, liquid cooling enables greater heat capture and reuse, allowing operators to recover a larger fraction of thermal energy that would otherwise be rejected into the environment.

Co-Designing Cooling and Chips

The trend of integrated design and simultaneous development is not new to the Mikros Technologies team. An early example of integrated thermal-mechanical design and joint optimization included single-phase and two-phase liquid cooling technologies developed for NASA electronics and cabin temperature control in the 1990s. These advanced thermal management solutions could operate under extreme heat fluxes, while meeting stringent constraints for mass, volume, vibration, and system reliability. Success demanded more than simply optimizing the cooling hardware. Thermal architectures, mechanical structures, manufacturing approaches, and system-level requirements were developed in parallel to achieve performance objectives within tightly constrained operating environments. The resulting solutions delivered reliable thermal control in mission-critical applications where temperature management directly influences functionality, operational readiness, reliability, and safety. Today, the engineering principles are the same, shifted from spacecraft to AI accelerators. Our engineers collaborate with semiconductor manufacturers on chip-to-cooling co-optimization, using thermal simulation, experimental validation, and innovative microchannel cooling architectures to align package architecture, power delivery, heat acquisition, and coolant distribution strategies. This integrated development process enables higher allowable chip power, lower junction temperatures, improved thermal uniformity, and manufacturable cooling solutions for today's and next-generation AI and HPC devices. An example of this is Mikros Technologies' work cooling Broadcom's 3.5D XDSiP platform.

![](/dam/jcr:7ee851f3-2b16-4994-847d-387f662ebb10/Mikros-XPU-Cold-Plate_IMG_5300-Edit%20(1)%20(1).2026-10-20-03-40-46.png)

*Mikros Technologies co-designed a custom cold plate for Broadcom's 3.5D XDSiP.*

Critical Parameters in Direct Liquid Cooling

Coolant inlet temperature dominated headlines at CES 2026 when Nvidia CEO Jensen Huang announced the Vera Rubin AI platform can operate at 45°C (113°F) inlet coolant temperatures. The idea of cooling supercomputers with "hot water" sent shockwaves through Wall Street, but this information was no surprise to thermal engineers, who have long recognized that increasing coolant temperature is a powerful mechanism for improving facility efficiency, reducing chiller dependence, and enabling higher performance liquid cooling systems. While coolant inlet temperature has emerged as a highly visible metric, it is only one of several critical design parameters that govern direct liquid cooling performance. Engineers must simultaneously optimize thermal resistance, flow distribution, heat transfer coefficients, and pressure drop, while refining cold plate architectures to maximize heat removal and minimize pumping and cooling power. Together, these thermal constraints determine the ability to maintain acceptable junction temperatures, improve system efficiency, and operate with elevated coolant temperatures. Regardless of whether the target device is a CPU, GPU, XPU, ASIC, network switch, or other high-power electronic component, the underlying objective remains the same: maximize heat extraction while minimizing thermal resistance, pumping and cooling power, and system complexity. As power densities continue to increase and acceptable thermal margins shrink, optimization of these thermal-fluid design variables is no longer sufficient on its own. The industry must now address a new challenge: translating advanced cooling architectures from engineered solutions into manufacturable products that can be produced and deployed at scale.

![](/dam/jcr:12a816b4-378b-43ca-8d55-cc3418455e34/People_Josh%20Testing.2026-10-20-03-40-17.jpg)

*Mikros Technologies builds application-specific test platforms that simulate deployment conditions and verify thermal performance.*

Shifting from Thermal Design to Scalable Deployment

As power densities continue to increase, the challenge facing the industry extends beyond thermal performance alone. AI infrastructure deployment requires cooling technologies that can be manufactured repeatedly, integrated consistently, and supported across thousands of data centers. The ability to maintain thermal performance at scale has become just as important as the performance specifications themselves. This shift is driving a new set of engineering priorities. Cold plates must not only deliver low thermal resistance and low pressure drop, but also be manufacturable with high yields, repeatable performance, and predictable cost structures. Materials, machining processes, joining methods, leak testing, verification, and quality control procedures influence the success of a cooling technology. As deployments expand from individual servers to enterprise-scale clusters and AI factories, reliability, supply chain readiness, and production capacity become critical design considerations. Long before liquid cooling became a requirement for AI data centers, Mikros Technologies had set the benchmarks, developing best-in-class thermal management solutions capable of dissipating heat fluxes exceeding 1 kW/cm², achieving thermal resistance below 0.02°C·cm²/W, and maintaining pressure drops below 20 kPa at full thermal load, all while minimizing pumping and power requirements. These capabilities combined with deep expertise in microchannel architectures and thermal engineering drove Jabil's acquisition of the company in October 2024. This strategic alliance helped support their existing customer base as well as ours. For Jabil, manufacturing at scale is table stakes. The combination of Mikros Technologies' thermal management intellectual property with Jabil's global manufacturing footprint, supply chain infrastructure, and production expertise, rapidly enables the transition of advanced cooling architectures from engineering prototypes to high-volume manufacturing. The result is thermal infrastructure that delivers repeatable thermal and hydraulic performance, robust quality control, supply chain resilience, and deployment readiness across enterprise-scale AI environments.

![](/dam/jcr:ef120654-536d-4c19-b13d-b806a65dba26/People_Engineering%20Team%202_2025%20(1)%20(2).2026-10-20-03-40-22.jpg)

*Mikros Technologies and Jabil are bridging thermal architecture development with manufacturing scale-up for enterprise deployment.*

The Future Is Performance at Scale

The evolution of liquid cooling reflects a broader transformation occurring across the AI ecosystem. What began as a thermal management challenge has become a critical element of semiconductor architecture, system design, and data center deployment strategy. As chip power continues to rise and AI infrastructure scales toward megawatt-class deployments, cooling can no longer be treated as a supporting subsystem; it has become an enabling technology that directly influences performance, reliability, scalability, and efficiency. Ultimately, organizations that can tightly co-optimize cooling technologies with chip design, packaging, and data center infrastructure will define the next frontier. **About the Author** *Joe Sullivan is Senior Engineering and Product Development Manager at [Mikros Technologies](/), a Jabil company, leading cross-functional teams from requirements scoping through pilot production to deliver advanced liquid cooling solutions for high-performance computing, AI, and semiconductor test customers. Joe holds a PhD in Mechanical Engineering from MIT, an MS in Civil \& Environmental Engineering (Atmosphere/Energy) from Stanford University, and a BS in Mechanical Engineering from Cornell University.* *This article was first published in [Global SMT \& Packaging](https://smt-pcb-electronics-manufacturing-news.globalsmt.net/books/wcoz/#p=1), Vol. 26, Number 5.*



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